1. Field of the Invention
The present invention relates to a driving method of a plasma display panel.
2. Discussion of the Related Art
The plasma display panel (PDP) has been receiving substantial attention since the PDP has higher resolution, a higher rate of emission efficiency, and a wider view angle in comparison to other flat panel displays. The PDP is a flat panel display for showing characters or images using plasma generated by gas discharge, and includes more than hundreds of thousands to millions of pixels in a matrix format, in which the number of pixels are determined by the size of the PDP. With reference to FIG. 1, a configuration of the PDP will be described.
FIG. 1 shows a partial perspective view of the PDP.
As shown in FIG. 1, the PDP includes two substrates 1 and 6 that face each other with a gap therebetween. Pairs of scan electrodes 4 and sustain electrodes 5 are formed in parallel on the first glass substrate 1, and the scan electrodes 4 and the sustain electrodes 5 are covered with a dielectric layer 2 and a protection film 3. A plurality of address electrodes 8 are formed on the second glass substrate 6, and the address electrodes 8 are covered with an insulator layer 7. Barrier ribs 9 are formed in parallel with the address electrodes 8 on the insulator layer 7 between the address electrodes 8, and phosphors 10 are formed on the surface of the insulator layer 7 and on both sides of the barrier ribs 9. The glass substrates 1 and 6 are provided facing each other with discharge spaces 11 between the glass substrates 1 and 6 so that the scan electrodes 4 and the sustain electrodes 5 can cross the address electrodes 8. A discharge space 11 between the address electrode 8 and a crossing part of a pair of the scan electrode 4 and the sustain electrode 5 forms a discharge cell 12.
The electrodes of the PDP have an m×n matrix format. The address electrodes A1 to Am are arranged in the column direction, and n scan electrodes Y1 to Yn and sustain electrodes X1 to Xn are arranged in the row direction. The PDP operates with a frame divided into a plurality of subfields, and gray scales are represented by a combination of the subfields. Conventionally, each subfield has a reset period, an address period, and a sustain period.
Wall charges formed by a previous sustain-discharge are eliminated, and wall charges are established for performing a next address discharge properly in the reset period. Cells that are turned on (i.e., addressed cells) and cells that are turned off on the panel are selected, and wall charges are accumulated to the cells that are turned on in the address period. A sustain-discharge for substantially displaying images on the addressed cells is performed in the sustain period.
The term “wall charges” as used herein refer to charges that are formed on a wall of discharge cells neighboring each electrode and accumulated to electrodes. Although the wall charges do not actually touch the electrodes, it will be described that the wall charges are “generated,” “formed,” or “accumulated” thereon. Also, a wall voltage represents a potential difference formed on the wall of the discharge cells by the wall charges.
FIG. 2 shows conventional driving waveforms.
As shown in FIG. 2, a voltage at the scan electrode (i.e., Y electrode) is reduced to a voltage of VscL while a wall voltage between the scan electrode and the sustain electrode is maintained at a voltage which approximates a discharge firing voltage at the end of the reset period. In the address period, a scan pulse which has the voltage of VscL as a low peak voltage and a voltage of VscH as a high peak voltage is applied to the scan electrode in sequence, and a data pulse is applied to the address electrode at the same time so as to generate an address discharge.
The address discharge is determined by a density of priming particles and the wall voltage generated in the discharge space. For the first scan electrodes on the lower part of the panel, it takes longer to apply the scan pulse after the reset discharge is generated, and therefore the density of the priming particles is reduced. A voltage in the discharge space is gradually reduced and the wall voltage is eliminated on the lower part of the panel. Accordingly, an address margin is problematically reduced because it takes longer to discharge on the lower part of the panel than on the upper part of the panel.